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general description the MAX15040 high-efficiency switching regulator delivers up to 4a load current at output voltages from 0.6v to (0.9 x v in ). the device operates from 2.4v to 3.6v, making it ideal for on-board point-of-load and postregulation applications. total output-voltage accu- racy is within ?% over load, line, and temperature. the MAX15040 features 1mhz fixed-frequency pwm mode operation. the high operating frequency allows for small-size external components. the low-resistance on-chip nmos switches ensure high efficiency at heavy loads while minimizing critical parasitic inductances, making the layout a much simpler task with respect to discrete solutions. following a simple layout and footprint ensures first-pass success in new designs. the MAX15040 incorporates a high-bandwidth (> 15mhz) voltage-error amplifier. the voltage-mode control architecture and the voltage-error amplifier per- mit a type iii compensation scheme to achieve maxi- mum loop bandwidth, up to 200khz. high loop bandwidth provides fast transient response, resulting in less required output capacitance and allowing for all- ceramic capacitor designs. the MAX15040 features an output overload hiccup pro- tection and peak current limit on both high-side (sourc- ing current) and low-side (sinking and sourcing current) mosfets, for ultra-safe operations in case of high out- put prebias, short-circuit conditions, severe overloads, or in converters with bulk electrolytic capacitors. the MAX15040 features an adjustable output voltage. the output voltage is adjustable by using two external resistors at the feedback or by applying an external ref- erence voltage to the refin/ss input. the MAX15040 offers programmable soft-start time using one capacitor to reduce input inrush current. a built-in thermal shut- down protection assures safe operation under all condi- tions. the MAX15040 is available in a 2mm x 2mm, 16-bump (4 x 4 array), 0.5mm pitch wlp package. applications server power supplies point-of-load asic/cpu/dsp core and i/o voltages ddr power supplies base-station power supplies telecom and networking power supplies raid control power supplies features internal 15m? r ds(on) mosfets continuous 4a output current 1% output-voltage accuracy over load, line, and temperature operates from 2.4v to 3.6v supply adjustable output from 0.6v to (0.9 x v in ) adjustable soft-start reduces inrush supply current factory-trimmed 1mhz switching frequency compatible with ceramic, polymer, and electrolytic output capacitors safe startup into prebias output enable input/power-good output fully protected against overcurrent and overtemperature overload hiccup protection sink/source current in ddr applications 2mm x 2mm, 16-bump (4 x 4 array), 0.5mm pitch wlp package MAX15040 high-efficiency, 4a, step-down regulator with integrated switches in 2mm x 2mm package ________________________________________________________________ maxim integrated products 1 ordering information 19-4426; rev 2; 7/10 evaluation kit available part temp range pin-package m ax 15040e we + - 40c to + 85c 16 wlp + denotes a lead(pb)-free/rohs-compliant package. pin configuration appears at end of data sheet. output input 2.4v to 3.6v bst lx in en v dd gnd fb v dd comp pwrgd refin/ss gnd MAX15040 typical operating circuit for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
MAX15040 high-efficiency, 4a, step-down regulator with integrated switches in 2mm x 2mm package 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = v dd = 3.3v, t a = -40c to +85c. typical values are at t a = +25c, circuit of figure 1, unless otherwise noted.) (note 3) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, v dd , pwrgd to gnd ......................................-0.3v to +4.5v lx to gnd....................-0.3v to the lower of 4.5v or (v in + 0.3v) lx transient ..............(v gnd - 1.5v, <50ns), (v in + 1.5v, <50ns) comp, fb, refin/ss, en to gnd ..............-0.3v to the lower of 4.5v or (v dd + 0.3v) lx rms current (note 1) .........................................................5a bst to lx..................................................................-0.3v to +4v bst to gnd ..............................................................-0.3v to +8v continuous power dissipation (t a = +70c) 16-bump (4 x 4 array), 0.5mm pitch wlp (derated 12.5mw/ c above +70c)...........................1000mw operating temperature range ...........................-40c to +85c junction temperature ......................................................+150c continuous operating temperature at full load current (note 2) ...........................................+105c storage temperature range .............................-65c to +150c soldering temperature (reflow) .......................................+260c note 1: lx has internal clamp diodes to gnd and in. applications that forward bias these diodes should take care not to exceed the package power dissipation limit of the device. note 2: continuous operation at full current beyond +105c may degrade product life. parameter conditions min typ max units in/v dd in and v dd voltage range 2.40 3.60 v v in = 2.5v 0.52 1 in supply current no load, no switching v in = 3.3v 0.8 1.5 ma v in = 2.5v 3.7 5.5 v dd supply current no load, no switching v in = 3.3v 4 6 ma v in = v dd = 2.5v 12 total supply current (in + v dd ) no load v in = v dd = 3.3v 23 ma total shutdown current from in and v dd v in = v dd = v bst - v lx = 3.6v, v en = 0v 0.1 2 a v dd rising 2 2.2 v dd undervoltage lockout threshold lx starts/stops switching v dd falling 1.75 1.9 v v dd uvlo deglitching 2s bst t a = +25c 2 bst leakage current v bst = v dd = v in = 3.6v, v lx = 3.6v or 0v, v en = 0v t a = +85c 0.025 a pwm comparator pwm comparator propagation delay 10mv overdrive 10 ns comp comp clamp voltage high v dd = 2.4v to 3.6v 2.03 v comp clamp voltage low v dd = 2.4v to 3.6v 0.73 v comp slew rate 1.6 v/s pwm ramp valley v dd = 2.4v to 3.6v 830 mv pwm ramp amplitude 1v comp shutdown resistance from comp to gnd, v en = 0v 8 ?
MAX15040 high-efficiency, 4a, step-down regulator with integrated switches in 2mm x 2mm package _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = v dd = 3.3v, t a = -40c to +85c. typical values are at t a = +25c, circuit of figure 1, unless otherwise noted.) (note 3) parameter conditions min typ max units error amplifier fb regulation accuracy using internal reference 0.594 0.600 0.606 v open-loop voltage gain 1k ? from comp to gnd (note 4) 115 db error-amplifier unity-gain bandwidth series 5k ? , 100nf from comp to gnd (note 4) 26 mhz v dd = 2.4v to 2.6v 0 v dd - 1.80 error-amplifier common-mode input range v dd = 2.6v to 3.6v 0 v dd - 1.85 v v comp = 1.2v, sinking 500 error-amplifier minimum output current v comp = 1.0v, sourcing 1000 a fb input bias current v fb = 0.7v, using internal reference, t a = +25c -200 -100 na refin/ss refin/ss charging current v refin/ss = 0.45v 7 8 9 a refin/ss discharge resistance 520 ? v dd = 2.4v to 2.6v 0 v dd - 1.80 refin/ss common-mode range v dd = 2.6v to 3.6v 0 v dd - 1.85 v t a = +25c 30 v refin/ss offset voltage error amplifier offset -4.5 +4.5 mv lx (all bumps combined) v in = v bst - v lx = 2.5v 21 lx on-resistance, high side i lx = -0.4a v in = v bst - v lx = 3.3v 19 m ? v in = 2.5v 16 lx on-resistance, low side i lx = 0.4a v in = 3.3v 15 m ? high-side sourcing 5.5 7 lx peak current-limit threshold v in = 2.5v low-side sinking 5.5 7 a v lx = 0v -2 t a = +25c v lx = 3.6v +2 lx leakage current v in = 3.6v, v en = 0v t a = +85c 0.2 a lx switching frequency v in = 2.5v to 3.3v, t a = +25c 0.92 1 1.03 mhz lx maximum duty cycle v in = 2.5v to 3.3v, t a = +25c 92 96 % lx minimum on-time 80 ns rms lx output current 4a enable en input logic-low threshold 0.7 v en input logic-high threshold 1.7 v t a = +25c 1 en input current v en = 0 or 3.6v, v in = v dd = 3.6v t a = +85c 0.3 a
efficiency vs. output current MAX15040 toc01 output current (a) efficiency (%) 1 50 60 70 80 90 100 40 0.1 10 v dd = v in = 3.3v v out = 1.2v v out = 1.8v v out = 1.5v v out = 2.5v efficiency vs. output current MAX15040 toc02 output current (a) efficiency (%) 1 50 60 70 80 90 100 40 0.1 10 v in = v dd = 2.5v v out = 1.8v v out = 1.2v v out = 1.5v MAX15040 high-efficiency, 4a, step-down regulator with integrated switches in 2mm x 2mm package 4 _______________________________________________________________________________________ parameter conditions min typ max units thermal shutdown thermal-shutdown threshold rising +165 c thermal-shutdown hysteresis 20 c power-good (pwrgd) v fb falling, v refin/ss = 0.6v 87 90 93 power-good threshold voltage v fb rising, v refin/ss = 0.6v 92.5 % of v re f in /s s power-good edge deglitch v fb falling or rising 48 clock cycles pwrgd output-voltage low i pwrgd = 4ma (sinking) 0.03 0.15 v pwrgd leakage current v dd = v pwrgd = 3.6v, v fb = 0.9v 0.01 a overcurrent limit (hiccup mode) current-limit startup blanking 112 clock cycles restart time 896 clock cycles fb hiccup threshold v fb falling 70 % of v re f in /s s hiccup threshold blanking time v fb falling 36 s note 3: specifications are 100% production tested at t a = +25c. limits over the operating temperature range are guaranteed by design and characterization. note 4: guaranteed by design. electrical characteristics (continued) (v in = v dd = 3.3v, t a = -40c to +85c. typical values are at t a = +25c, circuit of figure 1, unless otherwise noted.) (note 3) typical operating characteristics (v in = v dd = 3.3v, output voltage = 1.8v, i load = 4a, and t a = +25c, circuit of figure 1, unless otherwise noted.)
MAX15040 high-efficiency, 4a, step-down regulator with integrated switches in 2mm x 2mm package _______________________________________________________________________________________ 5 efficiency vs. output current MAX15040 toc03 output current (a) efficiency (%) 1 50 60 70 80 90 100 40 0.1 10 v dd = 3.3v v in = 2.5v v out = 1.8v v out = 1.2v v out = 1.5v frequency vs. input voltage MAX15040 toc04 input voltage (v) frequency (mhz) 3.4 3.2 2.6 2.8 3.0 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 0.80 2.4 3.6 t a = -40 c t a = +25 c t a = +85 c line regulation MAX15040 toc05 input voltage (v) output voltage error (%) 3.4 3.2 3.0 2.8 2.6 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 2.4 3.6 v out = 1.8v v out = 1.2v load regulation MAX15040 toc06 load current (a) output voltage error (%) 3 2 1 -0.40 -0.30 -0.20 -0.10 0 0.10 -0.50 04 v out = 1.8v v out = 1.2v v out = 2.5v v out = 1.5v internal reference load-transient response MAX15040 toc07 40 s/div v out i out ac-coupled 100mv/div 0 1a/div switching waveforms MAX15040 toc08 400ns/div i lx v out v lx ac-coupled 50mv/div 0 0 2a/div 2v/div shutdown waveform MAX15040 toc09 10 s/div v en v out 2v/div 0 0 1v/div i out = 1.8a soft-start waveform MAX15040 toc10 400 s/div v en v out 2v/div 0 0 1v/div typical operating characteristics (continued) (v in = v dd = 3.3v, output voltage = 1.8v, i load = 4a, and t a = +25c, circuit of figure 1, unless otherwise noted.)
MAX15040 high-efficiency, 4a, step-down regulator with integrated switches in 2mm x 2mm package 6 _______________________________________________________________________________________ input shutdown current vs. input voltage MAX15040 toc11 input voltage (v) input shutdown current (na) 3.4 3.2 3.0 2.8 2.6 4 8 12 16 20 0 2.4 3.6 v en = 0 hiccup current limit MAX15040 toc12 1ms/div v out i in i out 1v/div 0 10a/div 5a/div 0 0 rms input current during short circuit vs. input voltage MAX15040 toc13 input voltage (v) rms input current (a) 3.4 3.2 3.0 2.8 2.6 0.1 0.2 0.3 0.4 0.5 0 2.4 3.6 v out = 0 feedback voltage vs. temperature MAX15040 toc14 temperature ( c) feedback voltage (v) 60 35 10 -15 0.592 0.594 0.596 0.598 0.600 0.602 0.604 0.606 0.608 0.610 0.590 -40 85 no load soft-start with refin/ss MAX15040 toc15 200 s/div i in v out v refin/ss 2a/div 0 0 0 0 v pwrgd 2v/div 500mv/div 1v/div typical operating characteristics (continued) (v in = v dd = 3.3v, output voltage = 1.8v, i load = 4a, and t a = +25c, circuit of figure 1, unless otherwise noted.) starting into prebias output with 2a load MAX15040 toc16 400 s/div v en i out v out 2v/div 0 0 0 0 v pwrgd 2v/div 1v/div 2a/div starting into prebias output with no load MAX15040 toc17 400 s/div v en v out 2v/div 0 0 0 v pwrgd 2v/div 1v/div
MAX15040 high-efficiency, 4a, step-down regulator with integrated switches in 2mm x 2mm package _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v in = v dd = 3.3v, output voltage = 1.8v, i load = 4a, and t a = +25c, circuit of figure 1, unless otherwise noted.) pin description bump name function a1, a2 gnd analog/power ground. connect gnd to the pcb ground plane at one point near the input bypass capacitor return terminal as close as possible to the device. a3, a4 in power-supply input. input supply range is from 2.4v to 3.6v. bypass in to gnd with a 22f ceramic capacitor in parallel to a 0.1 f ceramic capacitor as close as possible to the device. b1, b2, b3 lx inductor connection. all lx bumps are internally connected together. connect all lx bumps to the switched side of the inductor. lx is high impedance when the device is in shutdown mode. b4 v dd supply input. v dd powers the internal analog core. connect v dd to in with a 10 ? resistor. connect a 1f ceramic capacitor from v dd to gnd. c1 bst high-side mosfet driver supply. bypass bst to lx with a 0.1f capacitor. c2, c3 i.c. internally connected. leave unconnected or connect to ground. c4 en enable input. connect en to gnd to disable the device. connect en to v dd to enable the device. d1 pwrgd power-good output. pwrgd is an open-drain output that goes high impedance when v fb exceeds 92.5% of v refin/ss and v refin/ss is above 0.54v. pwrgd is internally pulled low when v fb falls below 90% of v refin/ss or v refin/ss is below 0.54v. pwrgd is internally pulled low when the device is in shutdown mode, v dd is below the internal uvlo threshold, or the device is in thermal shutdown. d2 fb feedback input. connect fb to the center tap of an external resistor-divider from the output to gnd to set the output voltage from 0.6v to 90% of v in . d3 comp voltage-error amplifier output. connect the necessary compensation network from comp to fb and the converter output (see the compensation design section). comp is internally pulled to gnd when the device is in shutdown mode. d4 refin/ss external reference input/soft-start timing capacitor connection. connect refin/ss to a system voltage to force fb to regulate to refin/ss voltage. refin/ss is internally pulled to gnd when the device is in shutdown and thermal shutdown mode. if no external reference is applied, the internal 0.6v reference is automatically selected. refin/ss is also used to perform soft-start. connect a minimum of 1nf capacitor from refin/ss to gnd to set the startup time (see the soft-start and reference input (refin/ss) section). starting into prebias output above nominal setpoint with no load MAX15040 toc18 1ms/div v en v out 2v/div 0 v pwrgd 2v/div 0 1v/div case temperature vs. ambient temperature MAX15040 toc19 ambient temperature ( c) case temperature ( c) 60 35 -15 10 -20 0 20 40 80 60 100 120 -40 -40 85 case = top side of device measured on a MAX15040evkit i out = 4a
MAX15040 high-efficiency, 4a, step-down regulator with integrated switches in 2mm x 2mm package 8 _______________________________________________________________________________________ block diagram control logic in lx gnd ilim threshold in bst thermal shutdown soft-start voltage reference bias generator oscillator 1v p-p shutdown control uvlo circuitry v dd shdn fb 0.9 x v refin/ss fb comp gnd pwrgd error amplifier pwm comparator current-limit comparator ilim threshold bst switch shdn lx comp clamps en refin/ss current-limit comparator MAX15040
MAX15040 c9 0.1 f optional c1 22 f output 1.8v/4a input 2.4v to 3.6v c3 0.1 f bst lx in v dd fb comp c12 33pf c11 820pf r4 5.1k ? r5 20k ? pwrgd l1 0.47 h c8 0.033 f c2 22 f c4 0.01 f c10 470pf r6 430 ? c5 1 f r1 10 ? refin/ss gnd v dd MAX15040 u1 in en on off bst lx lx r10 2.2 ? c15 1000pf gnd r3 8.06k ? 1% r7 4.02k ? 1% high-efficiency, 4a, step-down regulator with integrated switches in 2mm x 2mm package _______________________________________________________________________________________ 9 figure 1. all-ceramic capacitor design with v out = 1.8v detailed description the MAX15040 high-efficiency, voltage-mode switching regulator is capable of delivering up to 4a of output current. the MAX15040 provides output voltages from 0.6v to (0.9 x v in ) from 2.4v to 3.6v input supplies, making it ideal for on-board point-of-load applications. the output-voltage accuracy is better than 1% over load, line, and temperature. the MAX15040 features a 1mhz fixed switching frequen- cy, allowing the user to achieve all-ceramic capacitor designs and fast transient responses. the high operating frequency minimizes the size of external components. the MAX15040 is available in a 2mm x 2mm, 16-bump (4 x 4 array), 0.5mm pitch wlp package. the refin/ss function makes the MAX15040 an ideal solution for ddr and tracking power supplies. using internal low-r dson (15m ? ) n-channel mosfets for both high- and low-side switches maintains high efficiency at both heavy-load and high-switching frequencies. the MAX15040 employs voltage-mode control architec- ture with a high-bandwidth (> 15mhz) error amplifier. the op-amp voltage-error amplifier works with type iii compensation to fully utilize the bandwidth of the high- frequency switching to obtain fast transient response. adjustable soft-start time provides flexibilities to mini- mize input startup inrush current. an open-drain, power-good (pwrgd) output goes high impedance when v fb exceeds 92.5% of v refin/ss and v refin/ss is above 0.54v. pwrgd goes low when v fb falls below 90% of v refin/ss or v refin/ss is below 0.54v. controller function the controller logic block is the central processor that determines the duty cycle of the high-side mosfet under different line, load, and temperature conditions. under normal operation, where the current-limit and tem- perature protection are not triggered, the controller logic block takes the output from the pwm comparator and generates the driver signals for both high-side and low- side mosfets. the control logic block controls the break-before-make logic and the timing for charging the bootstrap capacitors. the error signal from the voltage- error amplifier is compared with the ramp signal generat- ed by the oscillator at the pwm comparator to produce the required pwm signal. the high-side switch turns on at the beginning of the oscillator cycle and turns off when the ramp voltage exceeds the v comp signal or the cur- rent-limit threshold is exceeded. the low-side switch then turns on for the remainder of the oscillator cycle. typical application circuit
MAX15040 high-efficiency, 4a, step-down regulator with integrated switches in 2mm x 2mm package 10 ______________________________________________________________________________________ current limit the internal, high-side mosfet has a typical 7a peak cur- rent-limit threshold. when current flowing out of lx exceeds this limit, the high-side mosfet turns off and the low-side mosfet turns on. the low-side mosfet remains on until the inductor current falls below the low- side current limit. this lowers the duty cycle and causes the output voltage to droop until the current limit is no longer exceeded. the MAX15040 uses a hiccup mode to prevent overheating during short-circuit output conditions. during current limit, if v fb drops below 70% of v refin/ss and stays below this level for typically 36s (12s min) or more, the device enters hiccup mode. the high-side mosfet and the low-side mosfet turn off and both comp and refin/ss are internally pulled low. the device remains in this state for 896 clock cycles and then attempts to restart for 112 clock cycles. if the fault-causing current limit has cleared, the device resumes normal operation. otherwise, the device reenters hiccup mode. soft-start and reference input (refin/ss) the MAX15040 utilizes an adjustable soft-start function to limit inrush current during startup. an 8a (typ) cur- rent source charges an external capacitor connected to refin/ss. the soft-start time is adjusted by the value of the external capacitor from refin/ss to gnd. the required capacitance value is determined as: where t ss is the required soft-start time in seconds. connect a minimum 1nf capacitor between refin/ss and gnd. refin/ss is also an external reference input (refin/ss). the device regulates fb to the voltage applied to refin/ss. the internal soft-start is not avail- able when using an external reference. figure 2 shows a method of soft-start when using an external refer- ence. if an external reference is not applied, the device uses the internal 0.6v reference. undervoltage lockout (uvlo) the uvlo circuitry inhibits switching when v dd is below 1.9v (typ). once v dd rises above 2v (typ), uvlo clears and the soft-start function activates. a 100mv hysteresis is built in for glitch immunity. bst the gate-drive voltage for the high-side, n-channel switch is generated by a flying-capacitor boost circuit. the capacitor between bst and lx is charged from the v in supply while the low-side mosfet is on. when the low-side mosfet is switched off, the voltage of the capacitor is stacked above lx to provide the necessary turn-on voltage for the high-side internal mosfet. power-good output (pwrgd) pwrgd is an open-drain output that goes high impedance when v fb is above 92.5% x v refin/ss and v refin/ss is above 0.54v. pwrgd pulls low when v fb is below 90% of v refin/ss for at least 48 clock cycles or v refin/ss is below 0.54v. pwrgd is low during shutdown. setting the output voltage the MAX15040 output voltage is adjustable from 0.6v to 90% of v in by connecting fb to the center tap of a resistor-divider between the output and gnd (figure 3). to determine the values of the resistor-divider, first select the value of r3 between 2k ? and 10k ? . then use the following equation to calculate r4: r4 = (v fb x r3)/(v out - v fb ) where v fb is equal to the reference voltage at refin/ss and v out is the output voltage. for v out = 0.6v, remove r4. if no external reference is applied at refin/ss, the internal reference is automatically select- ed and v fb becomes 0.6v. c at v ss = 8 06 . c r2 r1 refin/ss MAX15040 figure 2. typical soft-start implementation with external reference lx fb r3 r4 MAX15040 figure 3. setting the output voltage with a resistor voltage- divider
MAX15040 high-efficiency, 4a, step-down regulator with integrated switches in 2mm x 2mm package ______________________________________________________________________________________ 11 shutdown mode drive en to gnd to shut down the device and reduce quiescent current to less than 0.1a. during shutdown, lx is high impedance. drive en high to enable the MAX15040. thermal protection thermal-overload protection limits total power dissipation in the device. when the junction temperature exceeds t j = +165c, a thermal sensor forces the device into shut- down, allowing the die to cool. the thermal sensor turns the device on again after the junction temperature cools by 20c, causing a pulsed output during continuous overload conditions. the soft-start sequence begins after recovery from a thermal-shutdown condition. applications information in and v dd decoupling to decrease the noise effects due to the high switching frequency and maximize the output accuracy of the MAX15040, decouple v in with a 22f capacitor in parallel with a 0.1f capacitor from v in to gnd. also decouple v dd with a 1f capacitor from v dd to gnd. place these capacitors as close as possible to the device. inductor selection choose an inductor with the following equation: where lir is the ratio of the inductor ripple current to full load current at the minimum duty cycle and f s is the switching frequency (1mhz). choose lir between 20% to 40% for best performance and stability. use an inductor with the lowest possible dc resistance that fits in the allotted dimensions. powdered iron or ferrite core types are often the best choice for performance. with any core material, the core must be large enough not to saturate at the current limit of the MAX15040. output-capacitor selection the key selection parameters for the output capacitor are capacitance, esr, esl, and voltage-rating requirements. these affect the overall stability, output ripple voltage, and transient response of the dc-dc converter. the out- put ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitors esr, and the voltage drop due to the capacitors esl. estimate the output voltage ripple due to the output capacitance, esr, and esl as follows: where the output ripple due to output capacitance, esr, and esl is: or whichever is higher. the peak-to-peak inductor current (i p-p ) is: use these equations for initial output capacitor selec- tion. determine final values by testing a prototype or an evaluation circuit. a smaller ripple current results in less output voltage ripple. since the inductor ripple current is a factor of the inductor value, the output voltage rip- ple decreases with larger inductance. use ceramic capacitors for low esr and low esl at the switching frequency of the converter. the ripple voltage due to esl is negligible when using ceramic capacitors. load-transient response depends on the selected out- put capacitance. during a load transient, the output instantly changes by esr x ? i load . before the con- troller can respond, the output deviates further, depending on the inductor and output capacitor val- ues. after a short time, the controller responds by regu- lating the output voltage back to its predetermined value. the controller response time depends on the closed-loop bandwidth. a higher bandwidth yields a faster response time, preventing the output from deviat- ing further from its regulating value. see the compen- sation design section for more details. i vv fl x v v pp in out s out in ? = ? v ripple esl ( ) ) = ? i t x esl pp off v i t x esl or ripple esl pp on () = ? vix ripple esr p p () = ? e esr v i xc xf ripple c pp out s () = ? 8 vv vv ripple ripple c ripple esr ripple esl =+ + () () () l vvv f v lir i out in out s in out max = ? () ()
MAX15040 high-efficiency, 4a, step-down regulator with integrated switches in 2mm x 2mm package input-capacitor selection the input capacitor reduces the current peaks drawn from the input power supply and reduces switching noise in the device. the total input capacitance must be equal to or greater than the value given by the fol- lowing equation to keep the input ripple voltage within the specification and minimize the high-frequency rip- ple current being fed back to the input source: where v in-ripple is the maximum allowed input ripple voltage across the input capacitors and is recommend- ed to be less than 2% of the minimum input voltage, d is the duty cycle (v out /v in ), and t s is the switching period (1/f s ) = 1s. the impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source, but are instead shunted through the input capacitor. the input capacitor must meet the ripple current requirement imposed by the switching currents. the rms input ripple current is given by: where i ripple is the input rms ripple current. compensation design the power transfer function consists of one double pole and one zero. the double pole is introduced by the inductor, l, and the output capacitor, c o . the esr of the output capacitor determines the zero. the double pole and zero frequencies are given as follows: where r l is equal to the sum of the output inductors dc resistance (dcr) and the internal switch resistance, r dson . a typical value for r dson is 15m ? . r o is the output load resistance, which is equal to the rated output voltage divided by the rated output current. esr is the total equivalent series resistance of the output capacitor. if there is more than one output capacitor of the same type in parallel, the value of the esr in the above equa- tion is equal to that of the esr of a single output capaci- tor divided by the total number of output capacitors. the MAX15040 high switching frequency allows the use of ceramic output capacitors. since the esr of ceramic capacitors is typically very low, the frequency of the associated transfer function zero is higher than the unity- gain crossover frequency, f c , and the zero cannot be used to compensate for the double pole created by the output inductor and capacitor. the double pole produces a gain drop of 40db/decade and a phase shift of 180. the compensation network must compensate for this gain drop and phase shift to achieve a stable high-band- width closed-loop system. therefore, use type iii com- pensation as shown in figure 4 and figure 5. type iii compensation possesses three poles and two zeros with the first pole, f p1_ea , located at zero frequency (dc). locations of other poles and zeros of the type iii compen- sation are given by: the above equations are based on the assumptions that c1 >> c2, and r3 >> r2, which are true in most appli- cations. placements of these poles and zeros are deter- mined by the frequencies of the double pole and esr zero of the power transfer function. it is also a function of the desired closed-loop bandwidth. the following section outlines the step-by-step design procedure to calculate the required compensation components for the MAX15040. the output voltage is determined by: for v out = 0.6v, r4 is not needed. r r v out 4 06 3 06 = ? () . . f xr xc pea 1 223 2_ = f x pea 3 1 2 _ = r rxc 12 f xr xc zea 2 1 233 _ = f xr xc zea 1 1 211 _ = f x esr x c z esr o _ = 1 2 ff xlxc x r esr rr plc p lc o o ol 12 1 2 __ == + + ? ? ? ? ? ? ii vvv v ripple load out in out in = ? () c dxt xi v in min sout in ripple _ = ? 12 ______________________________________________________________________________________
MAX15040 the zero-cross frequency of the closed-loop, f c , should be between 10% and 20% of the switching frequency, f s (1mhz). a higher zero-cross frequency results in faster transient response. once f c is chosen, c1 is cal- culated from the following equation: where v p-p = 1v p-p (typ). due to the underdamped nature of the output lc dou- ble pole, set the two zero frequencies of the type iii compensation less than the lc double-pole frequency to provide adequate phase boost. set the two zero fre- quencies to 80% of the lc double-pole frequency. hence: setting the second compensation pole, f p2_ea , at f z_esr yields: set the third compensation pole at 1/2 of the switching frequency (500khz) to gain phase margin. calculate c2 as follows: the above equations provide accurate compensation when the zero-cross frequency is significantly higher than the double-pole frequency. when the zero-cross frequen- cy is near the double-pole frequency, the actual zero- cross frequency is higher than the calculated frequency. in this case, lowering the value of r1 reduces the zero- cross frequency. also, set the third pole of the type iii compensation close to the switching frequency (1mhz) if the zero-cross frequency is above 200khz to boost the phase margin. the recommended range for r3 is 2k ? to 10k ? . note that the loop compensation remains unchanged if only r4s resistance is altered to set differ- ent outputs. soft-starting into a prebiased output the MAX15040 soft-starts into a prebiased output without discharging the output capacitor. in safe prebiased start- up, both low-side and high-side switches remain off to avoid discharging the prebiased output. pwm operation starts when the voltage on refin/ss crosses the voltage on fb. the pwm activity starts with the low-side switch turning on first to build the bootstrap capacitor charge. power-good (pwrgd) asserts 48 clock cycles after fb crosses 92.5% of the final regulation set point. after 4096 clock cycles, the device switches from prebiased safe startup mode to forced pwm mode. the MAX15040 is capable of starting into a prebias volt- age higher than the nominal set point without abruptly dis- charging the output. this is achieved by using the sink current control of the low-side mosfet, which has four internally set sinking current-limit thresholds. an internal 4-bit dac steps through these thresholds, starting from the lowest current limit to the highest, in 128 clock cycles on every power-up. c xr x f s 2 1 1 = r c x esr c o 2 3 = c xr x l x c x r esr rr oo lo 3 1 08 3 = + + . () r xc x l x c x r esr rr oo lo 1 1 08 1 = + + . () c v v xxrx r r f in pp l o c 1 25 231 = ? ? ? ? ? ? + ? . () high-efficiency, 4a, step-down regulator with integrated switches in 2mm x 2mm package ______________________________________________________________________________________ 13 l c out v out r3 r4 r1 comp fb lx c1 c3 r2 c2 MAX15040 figure 4. type iii compensation network double pole gain (db) freuenc (hz) second pole first and second zeros power-stage transfer function compensation transfer function open-loop gain third pole figure 5. type iii compensation illustration
MAX15040 high-efficiency, 4a, step-down regulator with integrated switches in 2mm x 2mm package 14 ______________________________________________________________________________________ pcb layout considerations and thermal performance careful pcb layout is critical to achieve clean and stable operation. it is highly recommended to duplicate the MAX15040 evaluation kit layout for optimum performance. if deviation is necessary, follow these guidelines for good pcb layout: 1) connect input and output capacitors to the power ground plane; connect all other capacitors to the sig- nal ground plane. 2) place capacitors on v dd , in, and refin/ss as close as possible to the device and the corresponding bump using direct traces. keep power ground plane and signal ground plane separate. 3) keep the high-current paths as short and wide as possible. keep the path of switching current short and minimize the loop area formed by lx, the out- put capacitors, and the input capacitors. 4) connect in, lx, and gnd separately to a large copper area to help cool the device to further improve efficiency and long-term reliability. 5) ensure all feedback connections are short. place the feedback resistors and compensation compo- nents as close to the device as possible. 6) route high-speed switching nodes, such as lx and bst, away from sensitive analog areas (fb, comp). chip information process: bicmos wlp gnd in in gnd a1 a2 a3 a4 b1 b2 b3 b4 c1 c2 c3 c4 d1 d2 d3 d4 lx lx v dd lx i.c. i.c. en bst pwrgd fb comp refin/ss (bumps on bottom) top view pin configuration package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package draw- ings may show a different suffix character, but the drawing per- tains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 wlp w162b2+1 21-0200
MAX15040 high-efficiency, 4a, step-down regulator with integrated switches in 2mm x 2mm package maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 1/09 initial release 1 5/10 revised the absolute maximum ratings and electrical characteristics . 1C4 2 7/10 revised the absolute maximum ratings .2

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